Computer Organization & Architecture — paper code N2113114, 60 marks, 2 hours. Every question from the only two NEP papers before your batch, cleaned and ranked: module first, topic second, with the min and max marks each topic has actually carried. Note on both papers: a calculator with a number-conversion function is not allowed — so conversions must be done by hand, and they are asked every time.
Estimated from PYQ coverage — ticking a topic means you can attempt its questions. Milestones: pass 27 · halfway 30 · distinction 45 · full paper 60.
Breathe. You do not need all 6 modules, and you do not need 60 out of 60. Passing lives around 27–30 marks out of 60. The plan below puts 30 marks on the table from just Q1 plus the fixed Q5 — so even with mistakes, you stay above the pass band. Add the safe set and it becomes 45 marks on the table.
| Learn | Where it pays | Marks on the table |
| Q1 — pick three | Number conversion + Associative memory + one more | 15 |
| Q5 — fixed slot | 8086 architecture + Booth's algorithm | 15 |
| Total on the table (minimum set) | 30 |
One more full question — cache mapping or non-restoring division (15) = 15 more marks. 30 + 15 = 45 out of 60, the distinction line.
Q1 (25 min) → Q5 (30) → strongest of Q3/Q4 (30) → check (15). Draw the 8086 diagram and the cache-mapping format once, neatly — they carry marks by themselves.
Honest note, not a guarantee. Pattern from only 2 papers, and COA rotates slots, so learn the topic, not the slot. It raises your odds; it is not a guarantee.
Q5 is identical in topic in both papers, in the same order: 8086 architecture (8) + Booth's algorithm (7). Learn those two and Q5 stops being a lottery — it is a ready-made 15 marks.
Q1 always holds number conversion and associative memory, with two rotating slots. The other big topics — non-restoring division, cache mapping, pipeline hazards, I/O methods, control unit, Flynn's — all appear both times but move slots between Q2, Q3, Q4 and Q6. Learn the topic, not the slot.
Exam dates are expected, not confirmed for AI & DS (taken from the AI & ML sheet: 17 / 19 / 21 / 25 / 27 Nov, 2:30–4:30 pm). Treat them as expected until the official sheet is seen.
MU sets this paper to a strict template. The table below is that template, read off both papers slot by slot. Below it is a model paper built from the template for practice — it is NOT the real exam paper, and no question in it is claimed to be a leaked or real question. Practise each slot with the Dec / May question listed in the ranked study below.
| Question | a (marks) | b (marks) | c (marks) | Evidence |
| Q1 — any 3 | Number conversion · Associative memory · Addressing modes / ISA-PCI-USB buses / Instruction pipeline / Memory characteristics — 5 marks each | Conversion + associative memory in Q1 both papers | ||
| Q2 | Non-restoring division or IEEE 754 (8) | Memory hierarchy or Pipeline hazards (7) | — | Topics rotate, marks fixed |
| Q3 | Cache mapping or Non-restoring division (8) | I/O methods (7) | — | I/O methods same slot both papers |
| Q4 | Microprogrammed CU or Cache mapping (8) | Pipeline hazards or Hardwired vs Softwired CU (7) | — | Topics rotate, marks fixed |
| Q5 — FIXED | 8086 architecture (8) | Booth's multiply (7) | — | Identical, both papers — FIXED |
| Q6 | Bus arbitration (Dec 5) or Flynn's (May 8) | Flynn's (Dec 5) or 80386DX modes (May 7) | Horizontal vs Vertical microinstruction (Dec 5 only) | Q6 shape changes: Dec 3 × 5, May 8 + 7 |
Q1 (any 3 × 5): a) number conversion (by hand) · b) associative memory · c) instruction pipeline · d) memory characteristics.
Q2 (8 + 7): a) IEEE 754 conversion · b) pipeline hazards.
Q3 (8 + 7): a) non-restoring division flowchart · b) I/O methods.
Q4 (8 + 7): a) cache mapping compare · b) hardwired vs softwired CU.
Q5 (8 + 7): a) 8086 architecture · b) Booth's multiply. — fixed slot, both papers.
Q6 (8 + 7): a) Flynn's classification · b) 80386DX modes.
If you can attempt Q1 + Q5 + any one of Q2–Q4 from this shape, you are attempting 45 marks with the most predictable material first.
Sorted by frequency and yield. Tick the boxes as you master each topic to watch your marks tracker update live.
The number systems everything else is built on: binary, octal and hexadecimal conversion, by hand.
Arithmetic in hardware: Booth's multiplication, non-restoring division, and IEEE 754 floating point.
The processor itself: the 8086, its addressing modes, and the two ways to build a control unit — hardwired and microprogrammed.
Where data lives: cache mapping, the memory hierarchy and its characteristics, and associative memory.
Getting data in and out: buses and arbitration, and the three data-transfer methods.
Pipelining and parallelism: pipeline stages and hazards, the 80386DX modes, and Flynn's classification.
Solutions for COA. Step-by-step solutions land here, one per question, in the same order as the ranked topics above.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Coming tomorrow — step-by-step, in this order.
Switch between subjects or jump straight to any section across Sem III.
This site is built for the full semester, not one page at a time. Every subject gets the same five attachments, in the same place.
| Subject | Ranked PYQs | Model paper | Pass plan | Exact papers | Solutions |
| Maths (N2113111) Computer · AI&DS · CS-IoT | Live — own page | Live — own page | Live — own page | Live — own page | From tomorrow |
| DSGT (N2113112) Computer · AI&DS · CS-IoT | Live — own page | Live — own page | Live — own page | Live — own page | From tomorrow |
| AOA (N2113113) Computer · AI&DS · CS-IoT | Live — own page | Live — own page | Live — own page | Live — own page | From tomorrow |
| COA (N2113114) Computer · AI&DS · CS-IoT | Live — on this page | Live — above | Live — above | Live — /papers/ hub | Live — on this page |
| Gen AI (OE, 2013311) Computer · AI&DS | Live — own page | Live — own page | Live — own page | Live — own page | From tomorrow |
Breathe. You do not need all 6 modules, and you do not need 60 out of 60. Passing lives around 27–30 marks out of 60. The plan below puts 30 marks on the table from just Q1 plus the fixed Q5 — so even with mistakes, you stay above the pass band. Add the safe set and it becomes 45 marks on the table.
| Learn | Where it pays | Marks on the table |
| Q1 — pick three | Number conversion + Associative memory + one more | 15 |
| Q5 — fixed slot | 8086 architecture + Booth's algorithm | 15 |
| Total on the table (minimum set) | 30 |
One more full question — cache mapping or non-restoring division (15) = 15 more marks. 30 + 15 = 45 out of 60, the distinction line.
Q1 (25 min) → Q5 (30) → strongest of Q3/Q4 (30) → check (15). Draw the 8086 diagram and the cache-mapping format once, neatly — they carry marks by themselves.
Honest note, not a guarantee. Pattern from only 2 papers, and COA rotates slots, so learn the topic, not the slot. It raises your odds; it is not a guarantee.